This invention relates to semiconductor memory devices, and more particularly to an N-channel silicon gate MOS read only memory or electrically programmable memory and processes for manufacture.
ROM and EPROM devices are manufactured by the methods disclosed in the patents and applications set forth below. While these methods are quite well developed, there is a continuing trend for smaller cell sizes and more dense cell arrays. The economics of manufacture of these devices, and of mounting them on circuit boards in the system, are such that the number of memory bits per semiconductor chip is advantageously as high as possible. ROMs and EPROMs of up to 32K bits (32768) are available at present. Standard sizes will progress through 64K, 128K, 256K and 1 megabit, dictating that cell sizes for the storage cells be quite small. Metal gate P-channel ROMs of small size can be relatively easily fabricated in the manner set forth in U.S. Pat. No. 3,541,543, assigned to Texas Instruments, but most microprocessor and computer parts are now made by the N-channel silicon gate process because of the shorter access times provided. In the past, the N-channel process has not been favorable to layout of ROM cells of the smallest size. N-channel ROMs are in some methods programmed by the presence or absence of a contact to the drain region; this requires a contact to each cell, and further metal-to-silicon contacts use excess space on the chip. EPROMs are typically made by the processes of U.S. Pat. No. 4,112,509 or 3,984,822. Again, the metal-to-silicon contacts represent a large fraction of the cell areas.
It is the principal object of this invention to provide a semiconductor ROM or EPROM memory cell of small size which uses a minumum of space for metal-to-silicon contacts, yet still is made by methods compatable with the standard high volume N-channel process. Another object is to provide a small-area MOS ROM or EPROM cell or the like, which is made by the standard N-channel self-aligned silicon gate manufacturing processes and is of small cell size and of a layout which provides high density cell arrays.